In semiconductor memory devices which are nonvolatile, information that is stored is not lost when the power supply is removed. Memory devices of this type include the EPROM (erasable programmable read only memory) and the EEPROM (electrically erasable programmable read only memory) One type of EPROM is a single transistor cell incorporating two polysilicon gates. The upper gate is the control gate and the bottom gate is a floating gate disposed between the control gate and the substrate. Programming or writing is accomplished by injection of hot electrons from the substrate through an oxide layer in response to a high applied drain voltage Erasure is accomplished by photoemission of hot electrons from the floating gate to the control gate and the substrate.
EEPROMs generally employ two element cells with two transistors Programming and erasure are accomplished by means of the Fowler-Nordheim effect which employs electrons that are tunneled through the energy barrier at the silicon-silicon oxide interface and into the oxide conduction band During a read operation, the state of the EEPROM cell is determined by current sensing by use of a select transistor.
The conventional nonvolatile split gate memory cell that has been used in the past required a self-aligned source-drain implant so that the cell area would be able to be reduced in size, to 30 .mu.m.sup.2 or less for example. Generally, such cells are programmed by channel injection of hot electrons and erased by Fowler-Nordheim tunneling or photoemission from the floating gate. The programming voltage required for operation of a split gate nonvolatile memory cell is much lower than those used for conventional EEPROMs.
The conventional split gate memory cell made by prior art processes includes a floating gate that is charged by injection of hot electrons from the channel disposed between the source and drain regions. A control gate is formed over the floating gate to control the portion of the channel region between the floating gate and the source in order to achieve split gate operation. The split gate structure is characterized by a coupling ratio which is not a fixed value.
In split gate memory devices, the floating gate is made to overlap the drain region so that the write function and programming can be implemented. If there is no overlap, or an actual underlap of the floating gate relative to the drain, write cannot be effectuated with hot electron injection and programming efficiency is reduced. In addition, these devices which employ the split gate configuration have the control gate overlapping the floating gate and extending over the channel to overlap the source region to enable turning on and driving the memory cell. In the conventional split gate process, the source and drain junctions generally were formed prior to the poly gate formation. Such prior art processes did not employ a fully self-aligned implant of the source and drain. Thus, the cell area size was extended and the transistor channel length increased.
In the conventional split gate memory cell, any misalignment of the source relative to the control gate affects the read current uniformity of the operating device. In order to avoid such misalignment, prior art devices have provided an overlap of the control gate to the source. Also, in some devices, the drain is self-aligned relative to the floating gate, but the source region is not self-aligned to the control gate, therefore, the channel length of this type of split gate device is not determinate, which adversely affected current dispersion in the memory cell during operation. In such cases where the total channel length is not a fixed distance, programming will also be adversely affected. If the total length varies, it is difficult to scale the dimensions of the layers, particularly to a short length which is desirable for high programming efficiency and reproducible cell current. If the length dimension is too large, then programming efficiency is not adequate, and the cell read current is reduced to the detriment of device operation. In addition, when an overlap is provided between the second polysilicon layer and the source, a substantial area is wasted and cell size becomes unnecessarily larger. Attempts to reduce the geometry and area size of split gate memory cells have met with difficulty due to limitations in the manufacturing process.
One prior art attempt to overcome the difficulties of misalignment of the source region to control gate and drain region to floating gate/control gate edges is described in an article entitled "A 128K Flash EEPROM Using Double-Polysilicon Technology", by Gheorghe Samachisa et al., which appeared in the IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pp. 676-683. In this article a structure is disclosed which illustrates self-aligned edges of the floating gate and control gate over the drain region and a self-aligned edge of the control gate over source region, however the process for producing such alignment is not disclosed. In addition, our process produces a device which avoids the disadvantages which are illustrated in FIG. 1(b) in the above-identified immediately preceding article, namely the pitting of the source region during the self-aligned etch, which results in poor surface topography. An abstract of the above-identified Samachisa et al. article appeared in the 1987 IEEE Solid-State Circuits Conference Digest of Technical Papers, Feb. 25, 1987, pp. 76 and 77, however it did not disclose our new process.